Keynotes HPCS2018
Bernd Mohr
Jülich Supercomputing Centre
Forschungszentrum Jülich, Jülich , Germany
NOTES (See file below. Forthcoming)
Thursday Keynote: Artificial Intelligence, HPC in the loop and Cyber-Physical Systems
Marc Duranton
Architecture, IC Design & Embedded Software Division
Commissariat à l’énergie atomique et aux énergies alternatives (CEA)
Paris-Saclay Campus - Nano-INNOV, 91191 Gif-sur-Yvette Cedex France
NOTES (See file below)
Thursday Closing Keynote: HPC Component Models
Christian Perez
Director of AVALON of the LIP, INRIA
Lyon, France
NOTES (See file below)
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Tuesday Keynote: Beyond Exascale through Non-von Neumann Architectures
Thomas Sterling
PI, Semantic Memory Architecture Research Team (SMART)
School of Informatics, Computing, and Engineering, Indiana University – Bloomington, IN, USA
ABSTRACT
The end of Moore’s Law and the flat-lining of per silicon die power consumption impose barriers to practical performance growth in the next decade even as the international community is forging ahead on many fronts to achieve exascale computing at the beginning of the next decade. The two legacies of several decades of performance growth that depended on exponential growth of silicon feature density and clock rate that are inhibiting future progress is the von Neumann architecture and static task scheduling and resource management. Advancement of future delivered performance may require the dramatic innovation in both areas. This presentation will describe the emerging non von Neumann architecture class, Continuum Computing Architecture, and the ParalleX execution model for dynamic adaptive control. It will demonstrate that through these advances peak performance may realize Zetaflops performance by the end of the next decade or before. It also shows the means for managing asynchronous computing and their use for general data analytics problems based on irregular time-varying graphs. Questions and comments will be welcome from the audience throughout the discussion.
SPEAKER BIOGRAPHY
Thomas Sterling holds the position of Professor of Electrical Engineering at the Indiana University (IU) School of Informatics, Computing, and Engineering as well as serves as the PI of the SMART group at the Department of Intelligence Systems Engineering. Since receiving his Ph.D. from MIT in 1984 as a Hertz Fellow, Dr. Sterling has engaged in applied research in parallel computing system structures, semantics, and operation in industry, government labs, and academia. Dr. Sterling is best known as the "father of Beowulf" for his pioneering research in commodity/Linux cluster computing for which he shared the Gordon Bell Prize in 1997. He led the HTMT Project sponsored by multiple agencies to explore advanced technologies and their implication for high-end computer system architectures. Other research projects in which he contributed included the DARPA DIVA PIM architecture project with USC-ISI, the DARPA sponsored HPCS program Cray-led Cascade Petaflops architecture, and the Gilgamesh high-density computing project at NASA JPL. Sterling is currently involved in research associated with the innovative ParalleX execution model for extreme scale computing to establish the foundation principles guiding the development of future generation Exascale computing systems. SMART is currently developing a radically new non-von Neumann architecture, Simultac, using active memory to accelerate dynamic graph computing applications. Dr. Sterling is the co-author of seven books and holds six patents. He was the recipient of the 2013 Vanguard Award and is a Fellow of the AAAS. Most recently, he co-authored the introductory textbook, “High Performance Computing”, published by Morgan-Kaufmann in December, 2017.
From Single Node to One Million HPC Cores
The International Conference on High Performance Computing & Simulation
(HPCS 2018)
The 16th Annual Meeting
July 16 – 20, 2018
Orléans, France
http://hpcs2018.cisedu.info/ or http://cisedu.us/rp/hpcs18
HPCS 2018 KEYNOTES
Tuesday Keynote: Beyond Exascale through Non-von Neumann Architectures
Thomas Sterling
PI, Semantic Memory Architecture Research Team (SMART)
School of Informatics, Computing, and Engineering, Indiana University – Bloomington, IN, USA
NOTES (See file below. Forthcoming)
Wednesday Keynote: Parallel Performance Analysis at Scale:
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Wednesday Keynote: Parallel Performance Analysis at Scale:
From Single Node to One Million HPC Cores
Bernd Mohr
Jülich Supercomputing Centre
Forschungszentrum Jülich, Jülich , Germany
Thursday Keynote: Artificial Intelligence, HPC in the loop and Cyber-Physical Systems
______________________________________________________________________
ABSTRACT
Current high-end HPC systems consist of complex configurations of potentially heterogeneous components. In addition, the hard- and software configuration can change dynamically due to fault recovering processes or power saving efforts. Deep hierarchies of large, complex software components are needed to operate and use them. Developing efficient and high-performance application software for these systems is challenging. Therefore, sophisticated performance measurement and analysis capabilities are required.
The talk will discuss the current state-of-the-art in freely available open-source parallel performance measurement and analysis tools. A special focus will be on the issues of portability, insightfulness, integration, and capability of performance tools. It will provide further details on the Score-P, Scalasca and Cube tools developed and maintained at Jülich Supercomputing Centre, one of the leading HPC computing centres hosting Europe's most parallel machine, a 458,752 core IBM BlueGene/Q. Next, some tool usage success stories will be presented. The talk will conclude with a discussion of current issues and potential future research opportunities.
SPEAKER BIOGRAPHY
Bernd Mohr started to design and develop tools for performance analysis of parallel programs already with his diploma thesis (1987) at the University of Erlangen in Germany, and continued this in his Ph.D. work (1987 to 1992). During a three year postdoc position at the University of Oregon, he designed and implemented the original TAU performance analysis framework. Since 1996 he has been a senior scientist at Forschungszentrum Jülich. Since 2000, he has been the team leader of the group ''Programming Environments and Performance Analysis''. Besides being responsible for user support and training in regard to performance tools at the Jülich Supercomputing Centre (JSC), he is leading the Scalasca performance tools efforts in collaboration with Prof. Felix Wolf of TU Darmstadt. Since 2007, he also serves as deputy head for the JSC division ''Application support''. He was an active member in the International Exascale Software Project (IESP/BDEC) and work package leader in the European (EESI2) and Juelich (EIC, ECL) Exascale efforts. For the SC and ISC Conference series, he serves on the Steering Committee. He is the author of several dozen conference and journal articles about performance analysis and tuning of parallel programs.
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Thursday Closing Keynote: HPC Component Models
Christian Perez
Director of AVALON of the LIP, INRIA
Lyon, France
Marc Duranton
Architecture, IC Design & Embedded Software Division
Commissariat à l’énergie atomique et aux énergies alternatives (CEA)
Paris-Saclay Campus - Nano-INNOV, 91191 Gif-sur-Yvette Cedex France
ABSTRACT
Computing systems are increasingly omnipresent and they interact directly with the physical world, both to extract information but also to influence it according to decision-making processes. These are the so-called "Cyber-Physical" systems. HPC systems will also be part of this evolution, simulating events in advance, predicting or controlling complex systems through simulation: we will have more and more "HPC in the loop". But computing has been developed mainly by not taking into account certain constraints of the physical world, such as temporal predictability: few computer languages deal explicitly with the notion of time, and our microprocessors have time behaviors that are difficult to predict. Understanding the natural environment is not obvious for a computer, and the so-called "deep learning" approach has revived Artificial Intelligence for processing natural signals, while introducing other problems. These will be part of the new challenges for the HPC systems of the future.
SPEAKER BIOGRAPHY
Marc Duranton is a member of the List institute of the Research and Technology Department of CEA (French Atomic Energy Commission), where he is involved in realizations for Deep Learning and on Cyber Physical Systems. He previously spent more than 23 years in Philips and Philips Semiconductors where he led the development of the family of L-Neuro chips, digital processors using artificial neural networks techniques. He also worked on several video coprocessors for the VLIW processor TriMedia and for various Nexperia platforms. In NXP Semiconductors, he was in charge of Ne-XVP project that targeted the design of the hardware and software of a multi-core processor for real-time applications and for consumer video processing. His interests include Deep Learning, Artificial Intelligence and emerging paradigms for computing systems, HPC, embedded systems, (Cognitive) Cyber Physical Systems, parallel architectures for high performance and real-time processing, models of computation and communication with time guaranties. He has published more than 35 patents and several book chapters. He is a member of the College of Ethics of CEA on "Moral issues in automatic decision-making processes". He is in charge of the roadmap activity of HiPEAC on High Performance and Embedded Architecture and Compilation, freely available at http://www.hipeac.net/roadmap.
ABSTRACT
Software component models emphasize the separation of concerns between the coding of building blocks and their composition into an application. It simplifies code re-use or replacement (for example testing a new implementation or algorithm) as well as it eases application deployment as its structure is known.
From the traditional software component point of view, this talk will cover the challenges of expressing HPC oriented patterns in such models to have both high performance and good software engineering properties. Several models and examples will be presented to illustrate the challenges on patterns such as parallel method invocations, collective operations, data sharing, task dependency as well as on higher level features such as hierarchy and genericity.
SPEAKER BIOGRAPHY
Christian Perez is a senior Inria researcher. Since 2011, he is leading the Inria-CNRS-ENSL-UCBL Avalon research team that focuses on algorithms and software architectures for parallel and distributed computing. His research interests include parallel and distributed programming models and runtime systems, software components, and deployment models. He is a member of the executive board of Grid’5000 large-scale and versatile testbed.